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A. Refereed Papers

  1. I-Jen Chao, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, Hsin-Wen Ting, "Analyses of Splittable Amplifier Technique and Cancellation of Memory Effect for Opamp Sharing," IEEE Transactions on VLSI Systems, DOI: 10.1109/TVLSI.2016.2586184, 2016.
    [SCI (IF: 1.245; rank: 132/257), EI | full text: pdf (?? MB) | IEEE-TVLSI]
  2. Yen-Long Lee, Soon-Jyh Chang, Yen-Chi Chen, and Yu-Po Cheng, "An Unbounded Frequency-Detection Mechanism for Continuous-rate CDR Circuits," IEEE Transactions on Circuits and Systems II: Express Briefs, DOI: 10.1109/TCSII.2016.2584106, 2016.
    [SCI (IF: 1.136; rank: 142/257), EI | full text: pdf (?? MB) | IEEE-TCAS-II]
  3. Chun-Po Huang, Hsin-Wen Ting, and Soon-Jyh Chang, "Analysis of Nonideal Behaviors Based on INL/DNL Plots for SAR ADCs," IEEE Transactions on Instrumentation and Measurement, vol.65, no.8, pp.1804-1817, Aug. 2016.
    [SCI (IF: 1.356; rank: 111/257), EI | full text: pdf (11.3 MB) | IEEE-TIM]
  4. Ya-Ting Shyu, Jai-Ming Lin, Che-Chun Lin, Chun-Po Huang, and Soon-Jyh Chang, "An Efficient and Effective Methodology to Control Turn-on Sequence of Power Switches for Power Gating Designs," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, DOI 10.1109/TCAD.2016.2523916, 2016.
    [SCI (IF: 1.181; rank: 137/257), EI | full text: pdf (4.5 MB) | IEEE-TCAD]
  5. Chun-Po Huang, Jai-Ming Lin, Ya-Ting Shyu, and Soon-Jyh Chang, "A Systematic Design Methodology of Asynchronous SAR ADCs," IEEE Transactions on VLSI Systems,vol.24, no.5, pp.1835-1848, May 2016.
    [SCI (IF: 1.245; rank: 132/257), EI | full text: pdf (5.38 MB) | IEEE-TVLSI]
  6. An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, and Soon-Jyh Chang, "A Capacitance-Ratio Quantification Design for Linearity Test in Differential Top-Plate Sampling SAR ADCs," International Journal of Circuit Theory and Applications, doi: 10.1002/cta.2014, 2014.
    [SCI (IF: 1.21; rank: 126/247), EI | full text: pdf (1.48 MB) | IJCTA]
  7. Peng-Yu Chen, Guan-Ying Huang, Ya-Ting Shyu, and Soon-Jyh Chang, "A Primary-Auxiliary Temperature Sensing Scheme for Multiple Hotspots in System-on-a-Chips," IEEE Sensors Journal, vol.14, no.8, pp.2633-2643, Aug. 2014.
    [SCI (IF: 1.852; rank: 71/247), EI | full text: pdf (2.56 MB) | IEEE-SJ]
  8. An-Sheng Chao, Cheng-Wu Lin, Hsin-Wen Ting, and Soon-Jyh Chang, "A Low-Cost Stimulus Design for Linearity Test in SAR ADCs," IEICE Transactions on Electronics, vol.E97-C, no.6, pp.538-545, Jun. 2014.
    [SCI (IF: 0.389; rank: 212/247), EI | full text: pdf (2.11 MB) | IEICE-TE]
  9. I-Jen Chao, Ching-Wen Hou, Bin-Da Liu, Soon-Jyh Chang, and Chun-Yueh Huang, "A Single Opamp Third-Order Low-Distortion Delta-Sigma Modulator with SAR Quantizer Embedded Passive Adder," IEICE Transactions on Electronics, vol.E97-C, no.6, pp.526-537, Jun. 2014.
    [SCI (IF: 0.389; rank: 212/247), EI | full text: pdf (3.46 MB) | IEICE-TE]
  10. Ya-Ting Shyu, Jai-Ming Lin, Chun-Po Huang, Cheng-Wu Lin, Ying-Zu Lin, and Soon-Jyh Chang, "An Effective and Efficient Approach for Power Reduction by Using Multi-Bit Flip-Flops," IEEE Transactions on VLSI Systems, vol. 21, no. 4, pp.624-635, Apr. 2013.
    [SCI (IF: 1.219; rank: 105/245), EI | full text: pdf (1.63 MB) | IEEE-TVLSI]
  11. Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, and Ying-Zu Lin, "10-bit 30-MS/s SAR ADC Using a Switchback Switching Method," IEEE Transactions on VLSI Systems, vol. 21, no. 3, pp.584-588, Mar. 2013.
    [SCI (IF: 1.219; rank: 105/245), EI | full text: pdf (732 KB) | IEEE-TVLSI]
  12. Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu, Yen-Ting Liu, and Soon-Jyh Chang, "A 9-bit 150-MS/s Subrange ADC Based on SAR Architecture in 90-nm CMOS," IEEE Transactions on Circuits and Systems - I, vol. 60, no. 3, pp.570-581, Mar. 2013.
    [SCI (IF: 1.970; rank: 52/245), EI | full text: pdf (2.14 MB) | IEEE-TCAS-I]
  13. Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang, and Soon-Jyh Chang, "Mismatch-Aware Common-Centroid Placement for Arbitrary-Ratio Capacitor Arrays Considering Dummy Capacitors," IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 31, no. 12, pp.1789-1802, Dec. 2012.
    [SCI (IF: 1.271; rank: 101/245), EI | full text: pdf (5.83 MB) | IEEE-TCAD]
  14. Ya-Ting Shyu, Ying-Zu Lin, Rong-Sing Chu, Guan-Ying Huang, and Soon-Jyh Chang, "A Low-Cost Bit-Error-Rate BIST Circuit for High-Speed ADCs Based on Gray Coding," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E95-A, no.12, pp.2415-2423, Dec. 2012.
    [SCI (IF: 0.226; rank: 223/245), EI | full text: pdf (2.51 MB) | IEICE-TF]
  15. Guan-Ying Huang, Soon-Jyh Chang, Chun-Cheng Liu, and Ying-Zu Lin, "1-uW 10-bit 200-kS/s SAR ADC with a Bypass Window for Biomedical Applications," IEEE Journal of Solid-State Circuits, vol.47, no.11, pp.2783-2795, Nov. 2012.
    [SCI (IF: 3.226; rank: 15/245), EI | full text: pdf (2.86 MB) | IEEE-JSSC]
  16. Ren-Li Chen and Soon-Jyh Chang, "A 6-bit Current-Steering DAC with Compound Current cells for Both Communication and Rail-to-Rail Programmable Voltage Source Applications," IEEE Transactions on Circuits and Systems - II, vol.46, no.11, pp.746-750, Nov. 2012.
    [SCI (IF: 1.320; rank: 85/246), EI | full text: pdf (1.03 MB) | IEEE-TCAS-II]
  17. I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Soon-Jyh Chang, Chun-Yueh Huang, and Hsin-Wen Ting, "A 3rd-Order Low-Distortion Delta-Sigma Modulator with Opamp Sharing and Relaxed Feedback Path Timing," IEICE Transactions on Electronics, vol.E95-C, no.11, pp.1799-1809, Nov. 2012.
    [SCI (IF: 0.400; rank: 201/245), EI | full text: pdf (2.66 MB) | IEICE-TE]
  18. Ren-Li Chen, Hsin-Wen Ting, and Soon-Jyh Chang, "Six-bit 2.7-GS/s 5.4-mW Nyquist Complementary Metal-Oxide Semiconductor Digital-to-Analogue Converter for Ultra-Wideband Transceivers," IET Circuits Devices & Systems, vol. 6, iss. 2, pp. 95-102, 2012
    [SCI (IF: 0.547; rank: 188/245), EI | full text: pdf (788 KB) | IET-CDS]
  19. Jin-Fu Lin, Soon-Jyh Chang, Te-Chieh Kung, Hsin-Wen Ting, and Chih-Hao Huang, "Transition-Code Based Linearity Test Method for Pipelined ADCs with Digital Error Correction," IEEE Transactions on VLSI Systems, vol. 19, no. 12, pp.2158-2169, Dec. 2011.
    [SCI (IF: 0.907; rank: 135/247), EI | full text: pdf (1.50 MB) | IEEE-TVLSI]
  20. Hsin-Wen Ting, Soon-Jyh Chang, and Su-Ling Huang, "A Design of Linearity Built-in Self-Test for Current-Steering DAC," Journal of Electronic Testing: Theory and Applications, vol. 27, pp.85-94, Feb. 2011.
    [SCI (IF: 0.500; rank: 182/247), EI | full text: pdf (901 KB) | JETTA]
  21. Jin-Fu Lin and Soon-Jyh Chang, "A Low-Power Mixed-Architecture ADC with Time-Interleaved Correlated Double Sampling Technique and Power-Efficient Back-End Stages," IEICE Transactions on Electronics, vol.E94-C, no.1, pp.89-101, Jan. 2011.
    [SCI (IF: 0.469; rank: 189/247), EI | full text: pdf (1.55 MB) | IEICE-TE]
  22. Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu, and Guan-Ying Huang, "An Asynchronous Binary-Search ADC Architecture with a Reduced Comparator Count," IEEE Transactions on Circuits and Systems - I, vol. 57, no. 8, pp.1829-1837, Aug. 2010.
    [SCI (IF: 1.420; rank: 80/246), EI | full text: pdf (1.30 MB) | IEEE-TCAS-I]
  23. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, and Ying-Zu Lin, "A 10-bit 50-MS/s SAR ADC with a Monotonic Capacitor Switching Procedure," IEEE Journal of Solid-State Circuits, vol.45, no.4, pp.731-740, Apr. 2010.
    [SCI (IF: 3.151; rank: 11/246), EI | full text: pdf (1.43 MB) | IEEE-JSSC]
  24. Jin-Fu Lin, Soon-Jyh Chang, Chun-Cheng Liu, and Chih-Hao Huang, "A 10-bit 60-MS/s Low-Power Pipelined ADC with Split-Capacitor CDS Technique," IEEE Transactions on Circuits and Systems - II, vol.57, no.3, pp.163-167, Mar. 2010.
    [SCI (IF: 1.320; rank: 85/246), EI | full text: pdf (809 KB) | IEEE-TCAS-II]
  25. Ying-Zu Lin, Cheng-Wu Lin, and Soon-Jyh Chang, "A 5-bit 3.2-GS/s Flash ADC with a Digital Offset Calibration Scheme," IEEE Transactions on VLSI Systems, vol.18, no.3, pp.509-513, Mar. 2010.
    [SCI (IF: 1.010; rank: 121/246), EI | full text: pdf (419 KB) | IEEE-TVLSI]
  26. Jin-Fu Lin, Soon-Jyh Chang, Chin-Fong Chiu, Hann-Huei Tsai, and Jiann-Jong Wang, "Low-Power and Wide-Bandwidth Cyclic ADC with Capacitor and Opamp Reuse Techniques for CMOS Image Sensor Application," IEEE Sensors Journal, vol.9, no.12, pp.2044-2054, Dec. 2009.
    [SCI (IF: 1.610; rank: 67/229), EI | full text: pdf (1.47 MB) | IEEE-SJ]
  27. Ying-Zu Lin, Soon-Jyh Chang, and Yen-Ting Liu, "A 5-bit 4.2-GS/s Flash ADC in 0.13-um CMOS Process," IEICE Transactions on Electronics, vol.E92-C no.2, pp.258-268, Feb. 2009.
    [SCI (IF: 0.608; rank: 154/229), EI | full text: pdf (1.01 MB) | IEICE-TE]
  28. Soon-Jyh Chang, Ying-Zu Lin, and Yen-Ting Liu, "A Digitally Calibrated CMOS Transconductor with a 100-MHz Bandwidth and 75-dB SFDR," IEEE Transactions on Circuits and Systems - II, vol.55, no.11, pp.1089-1093, Nov. 2008.
    [SCI (IF: 1.104; rank: 76/227), EI | full text: pdf (730 KB) | IEEE-TCAS-II]
  29. Hsin-Hung Ou, Bin-Da Liu, and Soon-Jyh Chang, "A 0.8-V 250-MSample/s Double-Sampled Inverse-Flip-Around Sample-and-Hold Circuit Based on Switched-Opamp Architecture," IEICE Transactions on Electronics, vol.E91-C, no.9, pp.1480-1487, Sep. 2008.
    [SCI (IF: 0.436; rank: 153/227), EI | full text: pdf (377 KB) | IEICE-TE]
  30. Chia-Ling Wei, Lu-Yao Wu, Hsiu-Hui Yang, Bin-Da Liu, Chien-Hung Tsai, and Soon-Jyh Chang, "A Versatile Step-Up/Step-Down Switched-Capacitor-Based DC-DC Converter," IEICE Transactions on Electronics, vol.E91-C, no.5, pp.809-812, May 2008.
    [SCI (IF: 0.436; rank: 153/227), EI | full text: pdf (136 KB) | IEICE-TE]
  31. Hsin-Hung Ou, Soon-Jyh Chang, and Bin-Da Liu, "Low-Power Circuit Techniques for Low-Voltage Pipelined ADCs Based on Switched-Opamp Architecture," IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences, vol.E91-A, no.2, pp.461-468, Feb. 2008.
    [SCI (IF: 0.287; rank: 173/227), EI | full text: pdf (499 KB) | IEICE-TF]
  32. Hsin-Wen Ting, Bin-Da Liu, and Soon-Jyh Chang, "Histogram Based Testing Method for Estimating A/D Converter Performance," IEEE Transactions on Instrumentation & Measurement, vol.57, no.2, pp.420-427, Feb. 2008.
    [SCI (IF: 0.832; rank: 106/227), EI | full text: pdf (218 KB) | IEEE-TIM]
  33. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, and Soon-Jyh Chang, "Oscillator-Based Reconfigurable Sinusoidal Signal Generator for ADC BIST," Journal of Electronic Testing: Theory and Applications, vol.23, pp.549-558, Dec. 2007.
    [SCI (IF: 0.232; rank: 170/206), EI | full text: pdf (395 KB) | JETTA]
  34. Soon-Jyh Chang, Chung Len Lee, and Jwu E Chen, "Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits," Journal of Information Science and Engineering, vol.19, no.4, pp.637-651, July 2003.
    [SCI (IF: 0.171; rank: 68/77), EI | full text: pdf (215 KB) | JISE]
  35. Soon-Jyh Chang, Chung Len Lee, and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Journal of Electronic Testing: Theory and Applications, vol.18, issue.2, pp.571-581, Dec. 2002.
    [SCI (IF: 0.196; rank: 152/200), EI | full text: pdf (352 KB) | JETTA]
  36. Soon-Jyh Chang, Chung Len Lee, and Jwu E Chen, "BIST Scheme for DAC Testing," Electronics Letters, vol.38, no.15, pp.776-777, July 18th, 2002.
    [SCI (IF: 0.970; rank: 52/200), EI | full text: pdf (278 KB) | IET-EL]

B. Conference papers

a.國際會議

    1. Wen-Tze Chen, Ya-Ting Shyu, Chun-Po Huang, and Soon-Jyh Chang, "The Pipelined ADC with Latched-Based Ring Amplifier," Proceedings of the 2016 IEEE International Symposium on Circuits and Systems, pp.85-88, 2016. (May 23-25, 2016, Montreal, Canada)
    2. Yen-Long Lee and Soon-Jyh Chang, "A 10-fJ/bit/dB Half-Rate Equalizer with Charge-Average Switched-Capacitor Summation Technique," Proceedings of the 2016 5th International Symposium on Next-Generation Electronics (ISNE), DOI: 10.1109/ISNE.2016.7543355, 2016. (May 3-6, 2016, Hsinchu, Taiwan)
    3. Yu-Po Cheng, Yen-Long Lee, Soon-Jyh Chang, and Ming-Hung Chien, "A 7 GB/S Half-Rate Clock and Data Recovery Circuit with Compact Control Loop," Proceedings of the 2016 IEEE International Symposium on VLSI Design, Automation & Test, DOI: 10.1109/VLSI-DAT.2016.7482531, 2016. (April 25-27, 2016, Hsinchu, Taiwan)
    4. Chia-Hsin Lee, Chih-Huei Hou, Chun-Po Huang, Soon-Jyh Chang, Yuan-Ta Hsieh, and Ying-Zong Juang, "A 2.5-bit/cycle 10-bit 160-MS/s SAR ADC in 90-nm CMOS Process," Proceedings of the 2016 IEEE International Symposium on VLSI Design, Automation & Test, DOI: 10.1109/VLSI-DAT.2016.7482525, 2016. (April 25-27, 2016, Hsinchu, Taiwan)
    5. Liang-Ying Lu, Ching-Yao Chang, Zhao-Hong Chen, Bo-Ting Yeh, Tai-Hua Lu, Peng-Yu Chen, Pin-Hao Tang, Kuen-Jong Lee, Lih-Yih Chiou, Soon-Jyh Chang, Chien-Hung Tsai, Chung-Ho Chen, Jai-Ming Lin, "A Testable and Debuggable Dual-Core System with Thermal-Aware Dynamic Voltage and Frequency Scaling," Proceedings of the 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), pp.17-18, 2016. (Jan. 25-28, 2016, Macao, China)
    6. Chun-Po Huang, Ya-Ting Shyu, Tsung-Yu Hsieh, Chieh-Wen Cheng, Wei-Chiun Liu, Hao-Ting Jian, Ying-Wei Wang, Bin-Da Liu, Soon-Jyh Chang, Lih-Yih Chiou, Chung-Ho Chen, "The SoC Design of a Versatile Biomedical Signal Processor for Potentiostat," Proceedings of the 2015 International Symposium on Bioelectronics and Bioinformatics (ISBB), pp.59-62, 2015. (Oct. 14-17, 2016, Beijing, China)
    7. Wei-Hao Tsai, Che-Hsun Kuo, Soon-Jyh Chang, Li-Tse Lo, Ying-Cheng Wu, "A 10-Bit 50-MS/s SAR ADC for Dual-Voltage Domain Portable Systems," Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, pp.2425-2428, 2015. (May 24-27, 2015, Lisbon, Portugal)
    8. Shuenn-Yuh Lee, Tzung-Min Tsai, Wei-Chih Lai, Soon-Jyh Chang, Stony Tai, "A 925 MHz 1.4uW Wireless Energy-harvesting Circuit with Error-correction ASK Demodulation for RFID Healthcare System," Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, pp.101-104, 2015. (May 24-27, 2015, Lisbon, Portugal)
    9. Jih-Ren Goh, Yen-Long Lee, and Soon-Jyh Chang, "A Dual-Edge Sampling CES Delay-Locked Loop Based Clock and Data Recovery Circuits," Proceedings of the 2015 IEEE International Symposium on VLSI Design, Automation & Test, DOI: 10.1109/VLSI-DAT.2015.7114500, 2015. (April 27-29, 2015, Hsinchu, Taiwan)
    10. Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, and Soon-Jyh Chang, "A First-Order Low Distortion Sigma-Delta Modulator Using Split DWA Technique and SAR Quantizer," Proceedings of the 2015 IEEE International Symposium on VLSI Design, Automation & Test, DOI: 10.1109/VLSI-DAT.2015.7114518, 2015. (April 27-29, 2015, Hsinchu, Taiwan)
    11. Kai-Hsiang Chiang, Soon-Jyh Chang, Guan-Ying Huang and Ying-Zu Lin, "A 10b 100kS/s SAR ADC with Charge Recycling Switching Method," Proceedings of the 2014 IEEE Asian Solid-State Circuits Conference, pp.329-332, 2014. (November 10-12, 2014, KaoHsiung, Taiwan)
    12. Tzung-Min Tsai, Hsing-Chen Lin, Shuenn-Yuh Lee and Soon-Jyh Chang, "Heart Rate Detection Through Bone-Conduction Headset," Proceedings of the 2014 IEEE Biomedical Circuits and Systems Conference, pp.65-68, 2014. (October 22-24, 2014, Lausanne, Switzerland)
    13. Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, Che-Hsun Kuo, "A 3.9-fJ/c.-S. 0.5-V 10-Bit 100-Ks/S Low Power SAR ADC with Time-Based Fixed Window," Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, pp.2345-2348, 2014. (June 1-5, 2014, Melbourne, Australia)
    14. Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Yen-Chi Chen, Jih Ren Goh, and Chung-Ming Huang, "An Area- and Power-Efficient Half-Rate Clock and Data Recovery Circuit," Proceedings of the 2014 IEEE International Symposium on Circuits and Systems, pp.2129-2132, 2014. (June 1-5, 2014, Melbourne, Australia)
    15. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low Power Pipelined SAR ADC with Loading-Free Architecture," Proceedings of the 2014 IEEE International Symposium on VLSI Design, Automation and Test, DOI: 10.1109/VLSI-DAT.2014.6834906, 2014. (April 28-30, 2014, Hsinchu, Taiwan)
    16. Shao-Hua Wan, Che-Hsun Kuo, Soon-Jyh Chang, Guan-Ying Huang, Chung-Po Huang, Goh Jih Ren, Kai-Tzeng Chiou and Cheng-Hsun Ho, "A 10-bit 50-MS/s SAR ADC with Techniques for Relaxing the Requirement on Driving Capability of Reference Voltage Buffers," Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, pp. 293-296, 2013. (November 11-13, 2013, Singapore)
    17. Guan-Ying Huang, Soon-Jyh Chang, Ying-Zu Lin, Chun-Cheng Liu and Chun-Po Huang, "A 10 b 200 MS/s 0.82 mW SAR ADC in 40 nm CMOS," Proceedings of the 2013 IEEE Asian Solid-State Circuits Conference, pp. 289-292, 2013. (November 11-13, 2013, Singapore)
    18. Ying-Zu Lin, Ya-Ting Shyu, Che-Hsun Kuo, Guan-Ying Huang, Chun-Cheng Liu, and Soon-Jyh Chang, "Multi-Step Switching Methods for SAR ADCs," Proceedings of the 10th International Conference on Sampling Theory and Applications, pp.552-555, 2013. (July 1-5, 2013, Bremen, Germany)
    19. I-Jen Chao, Chia-Ming Kuo, Bin-Da Liu, Chun-Yueh Huang, and Soon-Jyh Chang, "A 3rd-Order Delta-Sigma Modulator with Timing-Sharing Opamp-Sharing Technique," Proceedings of the 2013 IEEE International Symposium on Circuits & Systems, pp.2002-2005, 2013. (May 19-23, 2013, Beijing, China)
    20. Ting-Zi Chen, Soon-Jyh Chang, and Guan-Ying Huang, "A Successive Approximation ADC with Resistor-Capacitor Hybrid Structure," Proceedings of the 2013 IEEE International Symposium on VLSI Design, Automation & Test, DOI: 10.1109/VLDI-DAT.2013.6533842, 2013. (April 22-24, 2013, Hsinchu, Taiwan)
    21. Sheng-Hsiung Lin, Jin-Fu Lin, Guan-Ying Huang, and Soon-Jyh Chang, "A Pipelined SAR ADC with Loading-Separating Technique in 90-nm CMOS Technology," Proceedings of the 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp.264-267, 2012. (December 2-5, 2012, Kaohsiung, Taiwan)
    22. Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang, and Jin-Fu Lin, "A 1-V CDS Bandgap Reference without On-Chip Resistors," Proceedings of the 2012 IEEE Asia Pacific Conference on Circuits and Systems, pp.160-163, 2012. (December 2-5, 2012, Kaohsiung, Taiwan)
    23. Yen-Long Lee, Soon-Jyh Chang, Rong-Sing Chu, Ying-Zu Lin, Yen-Chi Chen, Goh Jih Ren, and Chung-Ming Huang, "A 5 Gb/s 1/4-rate Clock and Data Recovery Circuit Using Dynamic Stepwise Bang-bang Phase Detector," Proceedings of the 2012 IEEE Asian Solid-State Circuits Conference, pp.141-144. (November 12-13, 2012, Kobe, Japan)
    24. Cheng-Wu Lin, Chung-Lin Lee, Jai-Ming Lin, and Soon-Jyh Chang, "Analytical-Based Approach for Capacitor Placement with Gradient Error Compensation and Device Correlation Enhancement in Analog Integrated Circuits," Proceedings of the 2012 IEEE/ACM International Conference on Computer-Aided Design, pp. 635-642. (November 5-8, 2012, San Jose, California, USA)
    25. Chun-Po Huang, Soon-Jyh Chang, Guan-Ying Huang and Cheng-Wu Lin, "A Power-Efficient Sizing Methodology of SAR ADCs," Proceedings of the 2012 IEEE International Symposium on Circuits & Systems, pp.365-368. (May 20-23, 2012, Seoul, Korea)
    26. Peng-Yu Chen, Soon-Jyh Chang, Chung-Ming Huang and Chin-Fu Lin, "A 1-V, 44.6 ppm/oC Bandgap Reference with CDS Technique," Proceedings of the 2012 IEEE International Symposium on VLSI Design, Automation and Test, Digital Object Identifier: 10.1109/VLSI-DAT.2012.6212660. (April 23-25, 2012, Hsinchu, Taiwan)
    27. Cheng-Wu Lin, Cheng-Chung Lu, Jai-Ming Lin and Soon-Jyh Chang, "Routability-driven Placement Algorithm for Analog Integrated Circuits," Proceedings of the 2012 ACM International Symposium on Physical Design, pp.71-78. (March 25-28, 2012, Napa, California, USA)
    28. Ying-Zu Lin, Soon-Jyh Chang, Ya-Ting Shyu, Guan-Ying Huang, and Chun-Cheng Liu, "A 0.9-V 11-bit 25-MS/s Binary-Search SAR ADC in 90-nm CMOS," Proceedings of the 2011 IEEE Asian Solid-State Circuits Conference, pp.69-72, 2011. (November 14-16, 2011, Jeju, Korea)
    29. An-Sheng Chao, Soon-Jyh Chang and Hsin-Wen Ting, "A SAR ADC BIST for Simplified Linearity Test," Proceedings of the 2011 IEEE International SOC Conference, pp.146-149, 2011. (September 26-28, 2011, Taipei, Taiwan)
    30. Cheng-Wu Lin, Cheng-Chung Lu, Chun-Po Huang, Soon-Jyh Chang, and Jai-Ming Lin, "Routing-Aware Placement Algorithms for Modem Analog Integrated Circuits," Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, 2011. (August 7-10, 2011, Seoul, Korea)
    31. Po-Chun Hsiao, I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Chun-Yueh Huang and Soon-Jyh Chang, "A 9-bit 50 MS/s CBSC pipelined ADC using time-shifted correlated double sampling," Proceedings of the 54th IEEE International Midwest Symposium on Circuits and Systems, Paper Tp1A-2, 2011. (August 7-10, 2011, Seoul, Korea)
    32. Cheng-Wu Lin, Jai-Ming Lin, Yen-Chih Chiu, Chun-Po Huang and Soon-Jyh Chang, "Common-Centroid Capacitor Placement Considering Systematic and Random Mismatches in Analog Integrated Circuits," Proceedings of the 2011 IEEE Design Automation Conference, pp.528-533, 2011. (June 5-10, 2011, San Diego, California, USA)
    33. Tz-Jing Shau, Jin-Fu Lin, Soon-Jyh Chang and Chih-Hao Huang, "Conditional Capacitor Averaging Technique to Reduce Nonlinearity Induced by Capacitor Mismatch in 2.5-bit/stage Pipelined ADCs," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.139-142, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
    34. Chao-Fang Tsai, Wan-Jing Li, Peng-Yu Chen, Ying-Zu Lin and Soon-Jyh Chang, "On-Chip Reference Oscillators with Process, Supply Voltage and Temperature Compensation," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.108-111, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
    35. Chun-Po Huang, Ying-Zu Lin, Cheng-Wu Lin, Ya-Ting Shyu and Soon-Jyh Chang, "A Systematic Design Automation Approach for Flash ADCs," Proceedings of the 2010 IEEE International Symposium on Next-Generation Electronics, pp.81-84, 2010. (November 18-19, 2010, Kaohsiung, Taiwan)
    36. Tz-Jing Shau, Jin-Fu Lin and Soon-Jyh Chang, "Wide-Bandwidth Folded SHA With Sampling Capacitor Flip-Around Technique for Pipelined ADCs," Proceedings of the 2010 International Conference on High-Speed Circuits Designs, pp.86-89, 2010. (October 28-29, 2010, Taichung, Taiwan)
    37. I-Jen Chao, Chung-Lun Hsu, Bin-Da Liu, Chun-Yueh Huang, and Soon-Jyh Chang, "Behavior Model for Comparator-Based Switched-Capacitor SDM with Relaxed DEM Timing," Proceedings of the 2010 IEEE International Conference on Green Circuits and Systems, pp.495-498. EI DOI: 10.1109/ICGCS.2010.5543011. (June 21-23, 2010, Shanghai, China)
    38. Ying-Zu Lin, Chun-Cheng Liu, Guan-Ying Huang, Ya-Ting Shyu and Soon-Jyh Chang, "A 9-bit 150-MS/s 1.53-mW Subranged SAR ADC in 90-nm CMOS," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.243-244, 2010. (June 16-18, 2010, Honolulu, Hawaii, USA)
    39. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin and Chung-Ming Huang, "A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18um CMOS," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.241-242, 2010. (June 16-18, 2010, Honolulu, Hawaii, USA)
    40. Cheng-Wu Lin, Jai-Ming Lin, Chun-Po Huang and Soon-Jyh Chang, "Performance-driven Analog Placement Considering Boundary Constraint," Proceedings of the 2010 IEEE Design Automation Conference, pp.292-297, 2010. (June 13-18, 2010, Anaheim, California, USA)
    41. Ying-Zu Lin, Yu-Chang Lien and Soon-Jyh Chang, "A 0.35-1 V 0.2-3 GS/s 4-bit Low-Power Flash ADC for A Solar-Powered Wireless Module," Proceedings of the 2010 IEEE International Symposium on VLSI Design, Automation and Test, pp.299-302, 2010. (April 26-29, 2010, Hsinchu, Taiwan)
    42. Jing-Yi Huang, Chun-Hsun Wu, Le-Ren Chang-Chien and Soon-Jyh Chang, "Oscillation-Test Technique for Buck Voltage Regulator," Proceedings of the 2010 IEEE Applied Power Electronics Conference and Exposition, pp.1043-1047, 2010. (February 21-25, 2010, Palm Springs, California, USA)
    43. Chun-Cheng Liu, Soon-Jyh Chang, Guan-Ying Huang, Ying-Zu Lin, Chung-Ming Huang and Chih-Hao Huang, "A 10b 100MS/s 1.13mW SAR ADC with Binary Scaled Error Compensation," in IEEE ISSCC Dig. Tech. Papers, pp.386-387, 2010. (February 7-11, 2010, San Francisco, California, USA)
    44. An-Sheng Chao and Soon-Jyh Chang, "A Jitter Characterizing BIST with Pulse-Amplifying Technique," Proceedings of the 2009 IEEE Asian Test Symposium, pp.379-384, 2009. (November 23-25, 2009, Taichung, Taiwan)
    45. Jin-Fu Lin and Soon-Jyh Chang, "A Design-for-Test Circuit for the Reduced Code Based Linearity Test Method in Pipelined ADCs with Digital Error Correction Technique," Proceedings of the 2009 IEEE Asian Test Symposium, pp.57-62, 2009. (November 23-25, 2009, Taichung, Taiwan)
    46. Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin and Soon-Jyh Chang, "A 10-Bit 12-MS/s Successive Approximation ADC with 1.2-pF Input Capacitance," Proceedings of the 2009 IEEE Asian Solid-State Circuits Conference, pp.157-160, 2009. (November 16-18, 2009, Taipei, Taiwan)
    47. Ren-Li Chen and Soon-Jyh Chang, "A 5-bit 1.35-GSPS DAC for UWB Transceivers," Proceedings of the 2009 IEEE International Conference on Ultra-Wideband, pp.175-179, 2009. (September 9-11, 2009, Vancouver, Canada)
    48. Chun-Cheng Liu, Guan-Ying Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13um CMOS Process," in IEEE Symp. VLSI Circuits Dig. Tech. Papers, pp.236-237, 2009. (June 16-18, 2009, Kyoto, Japan)
    49. Hsin-Wen Ting, I-Jen Chao, Yu-Chang Lien, Soon-Jyh Chang and Bin-Da Liu, "A Low-Cost Output Response Analyzer Circuit for ADC BIST," Proceedings of the 2009 IEEE Circuits and Systems International Conference on Testing and Diagnosis, 2009, Digital Object Identifier: 10.1109/CAS-ICTD.2009.4960751. (April 28-29, 2009, Chengdu, China)
    50. Ya-Ting Shyu, Cheng-Wu Lin, Jin-Fu Lin and Soon-Jyh Chang, "A gm/ID-Based Synthesis Tool for Pipelined Analog to Digital Converters," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation and Test, pp.299-302, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
    51. Chun-Cheng Liu, Yi-Ting Huang, Guan-Ying Huang, Soon-Jyh Chang, Chung-Ming Huang and Chih-Haur Huang, "A 6-bit 220-MS/s Time-Interleaving SAR ADC in 0.18-um Digital CMOS Process," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation and Test, pp.215-218, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
    52. Yu-Chang Lien, Ying-Zu Lin and Soon-Jyh Chang, "A 6-bit 1GS/s Low-Power Flash ADC," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation and Test, pp.211-214, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
    53. Wan-Jing Li, Soon-Jyh Chang and Ying-Zu Lin, "A Current Compensated Reference Oscillator," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation and Test, pp.130-133, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
    54. Cheng-Wu Lin, Pin-Dai Sue, Ya-Ting Shyu and Soon-Jyh Chang, "A Bias-Driven Approach for Automated Design of Operational Amplifiers," Proceedings of the 2009 IEEE International Symposium on VLSI Design, Automation and Test, pp.118-121, 2009. (April 27-30, 2009, Hsinchu, Taiwan)
    55. Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu and Guan-Ying Huang, "A 5b 800MS/s 2mW Asynchronous Binary-Search ADC in 65nm CMOS," in IEEE ISSCC Dig. Tech. Papers, pp.80-81, 2009. (February 8-12, 2009, San Francisco, California, USA)
    56. Jin-Fu Lin, Te-Chieh Kung and Soon-Jyh Chang, "A Reduced Code Linearity Test Method for Pipelined A/D Converters," Proceedings of the 2008 IEEE Asian Test Symposium, pp.111-116, 2008. (November 24-27, 2008, Sapporo, Japan)
    57. Ying-Zu Lin, Cheng-Wu Lin and Soon-Jyh Chang, "A 2-GS/s 6-bit Flash ADC with Offset Calibration," Proceedings of the 2008 IEEE Asian Solid-State Circuits Conference, pp.385-388, 2008. (November 3-5, 2008, Fukuoka, Japan)
    58. Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A Power-Efficient 0.8-V, 9-bit, 20-MS/s Pipelined ADC with Opamp-Shared Loading-Free Architecture," Proceedings of the 2008 IEEE International Conference on Communications, Circuits and Systems, pp.1172-1175, 2008. (May 25-27, 2008, Xiamen, China)
    59. Hung-Yu Huang, Ying-Zu Lin and Soon-Jyh Chang, "A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture," Proceedings of the 2007 IEEE TENCON, no. ThSC-O4.1, 2007. (October 30 - November 2, 2007, Taipei, Taiwan)
    60. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A 5-bit 4.2-GS/s Flash ADC in 0.13-um CMOS Process," Proceedings of the 2007 IEEE Custom Integrated Circuits Conference, pp.213-216, 2007. (September 16-19, 2007, San Jose, California, USA)
    61. Tung-Hsing Wu, Yi-Lin Tsai and Soon-Jyh Chang, "An Efficient Design-for-Testability Scheme for Motion Estimation in H.264/AVC," Proceedings of the 2007 IEEE International Symposium on VLSI Design, Automation and Test, pp.236-239, 2007. (April 25-27, 2007, Hsinchu, Taiwan)
    62. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang and Soon-Jyh Chang, "An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders," Proceedings of the 2006 IEEE Asia-Pacific Conference on Circuits and Systems, pp.255-258, 2006. (December 4-7, 2006, Singapore)
    63. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Histogram Based Testing Strategy for ADCs," Proceedings of the 2006 IEEE Asian Test Symposium, pp.51-54, 2006. (November 20-23, 2006, Fukuoka, Japan)
    64. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A Digitally Calibrated Current-Voltage Feedback Transconductor in 0.13-um CMOS Process," Proceedings of the 2006 IEEE Asian Solid-State Circuits Conference, pp.159-162, 2006. (November 13-15, 2006, Hangzhou, China)
    65. Ying-Zu Lin, Yen-Ting Liu and Soon-Jyh Chang, "A 6-Bit 2-GS/s Flash Analog-to-Digital Converter in 0.18-um CMOS Process," Proceedings of the 2006 IEEE Asian Solid-State Circuits Conference, pp.351-354, 2006. (November 13-15, 2006, Hangzhou, China)
    66. Zhen-Guo Ding, Hsin-Hung Ou, Soon-Jyh Chang and Bin-Da Liu, "A 12-Bit, 135-MS/s Pipelined ADC Using Open-Loop Constant Gain Amplifier with Radix-Based Calibration," Proceedings of the 4th Regional Inter-University Postgraduate Electrical and Electronics Engineering Conference, pp.295-299, 2006. (July 13-14, 2006, Macau, China)
    67. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu and Soon-Jyh Chang, "An Easy Testable 2-D Transform Scheme in H.264 Advanced Video Coders," Proceedings of the 4th Regional Inter-University Postgraduate Electrical & Electronic Engineering Conference, pp.124-128, 2006. (July 13-14, 2006, Macau, China)
    68. Jin-Fu Lin and Soon-Jyh Chang, "A High Speed Pipelined Analog-to-Digital Converter Using Modified Time-Shifted Correlated Double Sampling Technique," Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp.5367-5370, 2006. (May 21-24, 2006, Island of Kos, Greece)
    69. Yen-Ting Liu, Lih-Yih Chiou and Soon-Jyh Chang, "Energy-Efficient Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop," Proceedings of the 2006 IEEE International Symposium on Circuits and Systems, pp.4329-4332, 2006. (May 21-24, 2006, Island of Kos, Greece)
    70. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu and Soon-Jyh Chang, "Reconstructive Oscillator Based Sinusoidal Signal Generator for ADC BIST," Proceedings of the 2005 IEEE Asian Solid-State Circuits Conference, pp.65-68, 2005. (November 1-3, 2005, Hsinchu, Taiwan)
    71. Ying-Zu Lin and Soon-Jyh Chang, "A CMOS Current-Voltage Feedback Transconductor with an 80-dB SFDR up to 100MHz," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.945-948, 2004. (December 6-9, 2004, Tainan, Taiwan)
    72. Chih-Haur Huang, Soon-Jyh Chang and Kuen-Jong Lee, "Design of High-Resolution Pipelined Analog-to-Digital Converters Using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.625-628, 2004. (December 6-9, 2004, Tainan, Taiwan)
    73. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "An On-Chip Concurrent High Frequency Analog and Digital Sinusoidal Signal Generator," Proceedings of the 2004 IEEE Asia-Pacific Conference on Circuits and Systems, pp.173-176, 2004. (December 6-9, 2004, Tainan, Taiwan)
    74. Chih-Haur Huang, Kuen-Jong Lee and Soon-Jyh Chang, "A Low-Cost Diagnosis Methodology for Pipelined A/D Converters," Proceedings of the 2004 IEEE Asian Test Symposium, pp.296-301, 2004. (November 15-17, 2004, Kenting, Taiwan)
    75. Hsin-Wen Ting, Bin-Da Liu and Soon-Jyh Chang, "A Time Domain Built-In Self-Test Methodology for SNDR and ENOB Tests of Analog-to-Digital Converters," Proceedings of the 2004 IEEE Asian Test Symposium, pp.52-57, 2004. (November 15-17, 2004, Kenting, Taiwan)
    76. Kuen-Jong Lee, Soon-Jyh Chang and Ruei-Shiuan Tzeng, "A Sigma-Delta Modulation Based BIST Scheme for A/D Converters," Proceedings of the 2003 IEEE Asian Test Symposium, pp.124-127, 2003. (November 17-19, 2003, Xian, China)
    77. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structure-Based Specification-Constrained Test Frequency Generation for Linear Analog Circuits," Proceedings of the 2002 IEEE International Mixed-Signal Test Workshop, pp.109-117, 2002. (June 19-21, 2002, Montreux, Switzerland)
    78. Chee-Kian Ong, Yeong-Jar Chang, Soon-Jyh Chang, Jiun-Liang Huang, Kuo-Chan Haung, Kwang-Ting Cheng and Wen-Ching Wu, "An Enhanced BIST Scheme for ADC and Non-monotonic DAC," Proceedings of the 2002 IEEE International Mixed-Signal Test Workshop, pp.171-180, 2002. (June 19-21, 2002, Montreux, Switzerland)
    79. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Proceedings of the 2002 IEEE European Test Workshop, pp.261-266, 2002. (May 26-29, 2002, Corfu, Greece)
    80. Sheng-Jer Kuo, Chung Len Lee, Soon-Jyh Chang and Jwu E Chen, "A DFT for semi-DC fault diagnosis for switched-capacitor circuits," Proceedings of the 1999 IEEE European Test Workshop, pp.58-63, 1999. (May 25-28, 1999, Constance, Germany)
    81. Soon-Jyh Chang, Chung Len Lee and Jwu E Chen, "Functional Test Pattern Generation for CMOS Operational Amplifier," Proceedings of the 1997 IEEE VLSI Test Symposium, pp.267-272, 1997. (April 27 - May 1, 1997, Monterey, California, USA)

    b.國內會議

    1. Tien-Feng Hsu, Chun-Po Huang, I-Jen Chao, and Soon-Jyh Chang, "A Comparator-Based OTA First-Order Low-Distortion Sigma-Delta Modulator with Split Data Weighted Averaging Algorithm Logic," Proceedings of the 25th VLSI Design/CAD Symposium. (August 5-8, 2014, Taichung, Taiwan)
    2. Jih-Ren Goh, Soon-Jyh Chang, and Yen-Long Lee, "A 0.5Gbps to 3.0 Gbps Dual-Edge Sampling CES DLL-CDR," Proceedings of the 25th VLSI Design/CAD Symposium. (August 5-8, 2014, Taichung, Taiwan)
    3. Yen-Chi Chen, Yen-Long Lee, Yu-Po Chang, and Soon-Jyh Chang, "A 0.5-to-4 Gbps Continuous Rate Clock and Data Recovery Circuit with Bi-directional Frequency Detection," Proceedings of the 25th VLSI Design/CAD Symposium. (August 5-8, 2014, Taichung, Taiwan)
    4. Jia-Jhang Wu, Soon-Jyh Chang, Sheng-Hsiung Lin, Chun-Po Huang, and Guan-Ying Huang, "Low Power and High Resolution Pipelined SAR ADC with Loading-Free Architecture," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
    5. Chao-Fang Tsai, Soon-Jyh Chang, and Ying-Zu Lin, "A 10-Bit 100-MS/s Power-Efficient Flash SAR ADC," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
    6. Kai-Tzeng Chiou and Soon-Jyh Chang, "A Speed Enhancing Technique for High-Speed Flash ADCs," Proceedings of the 24th VLSI Design/CAD Symposium. (August 6-9, 2013, Kaohsiung, Taiwan)
    7. Peng-Yu Chen, Guan-Ying Huang, Soon-Jyh Chang, and Ya-Ting Shyu, "Temperature Measuring Scheme for Multiple Hotspots in System Chips," Proceedings of the 7th VLSI Test Technology Workshop, S4-2. (July 15-17, 2013, Taipei, Taiwan)
    8. Cheng-Hsun Ho, Soon-Jyh Chang, Guan-Ying Huang, and Shao-Hua Wan, "A 0.5-V 10-bit 100-kS/s Asynchronous SAR ADC With Time-Based Fixed Window," Proceedings of the 23th VLSI Design/CAD Symposium. (August 7-10, 2012, Kenting, Taiwan)
    9. Ting-Zi Chen, Guan-Ying Huang, and Soon-Jyh Chang, "A 10-bit 50-MS/s Asynchronous SAR ADC with Low Input Capacitance," Proceedings of the 23th VLSI Design/CAD Symposium. (August 7-10, 2012, Kenting, Taiwan)
    10. I-Jen Chao, Wei-Chih Chen, Chia-Ming Kuo, Bin-Da Liu, Hsin-Wen Ting, Soon-Jyh Chang, and Chun-Yueh Huang, "A Low-Distortion Relaxed-DEM-Timing Delta-Sigma Modulator without Extra Adder in the Quantizer Input," Proceedings of the 22th VLSI Design/CAD Symposium, 2011. (August 2-5, 2011, Yunlin, Taiwan)
    11. Chien-Liang Kuo, and Soon-Jyh Chang, "A 20-MHz On-Chip Relaxation Oscillator," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 2011, Yunlin, Taiwan)
    12. Cheng-Wu Lin, Yen-Chih Chiu, Chun-Po Huang, Soon-Jyh Chang, and Jai-Ming Lin, "Mismatches-Aware Common-Centroid Placement for Capacitor Arrays," Proceedings of the 22th VLSI Design/CAD Symposium. (August 2-5, 2011, Yunlin, Taiwan)
    13. An-Sheng Chao, and Soon-Jyh Chang, "A SAR ADC BIST for Linearity Test Time Reduction," Proceedings of the 5th VLSI Test Technology Workshop, pp.59-63. (July 13-15, 2011, Nantou, Taiwan)
    14. Ren-Li Chen, Soon-Jyh Chang, and Hsin-Wen Ting, "A Low-Cost Low-Power Current-Steering DAC for UWB Transceivers," Proceedings of the 21th VLSI Design/CAD Symposium. (August 3-6, 2010, Kaohsiung, Taiwan)
    15. Chao-Fang Tsai, Wan-Jing Li, Peng-Yu Chen, Ying-Zu Lin, and Soon-Jyh Chang, "On-Chip Reference Oscillators with Process, Supply Voltage and Temperature Compensation," Proceedings of the 21th VLSI Design/CAD Symposium. (August 3-6, 2010, Kaohsiung, Taiwan)
    16. Guan-Ying Huang, Chun-Cheng Liu, Ying-Zu Lin, and Soon-Jyh Chang, "A 10-bit Low Input Capacitance SAR ADC," Proceedings of the 20th VLSI Design/CAD Symposium. (August 4-7, 2009, Hualien, Taiwan)
    17. Jin-Fu Lin and Soon-Jyh Chang, "An Improved Reduced Code Linearity Test Method for Pipelined A/D Converters," Proceedings of the 3rd VLSI Test Technology Workshop. (July 15-17, 2009, Nantou, Taiwan)
    18. Ying-Zu Lin, Cheng-Wu Lin, and Soon-Jyh Chang, "A Digitally Calibrated 5-bit 3.2-GS/s Flash ADC," Proceedings of the 19th VLSI Design/CAD Symposium. (August 5-8, 2008, Kenting, Taiwan)
    19. Jin-Fu Lin, Te-Chieh Kung, and Soon-Jyh Chang, "Linearity Testing of the Pipelined ADCs Using the Characteristic Observation Method," Proceedings of the 19th VLSI Design/CAD Symposium. (August 5-8, 2008, Kenting, Taiwan)
    20. Yu-Chang Lien, Hsin-Wen Ting, I-Chun Chen, Soon-Jyh Chang, and Bin-Da Liu, "A Low-Cost Sine-Wave Histogram Analyzer for ADC BIST," Proceedings of the 2nd VLSI Test Technology Workshop. (July 16-18, 2008, Tainan, Taiwan)
    21. Te-Chieh Kung, Jin-Fu Lin, and Soon-Jyh Chang, "Linearity Testing of the Pipelined ADCs Using the Characteristic Observation Method," Proceedings of the 2nd VLSI Test Technology Workshop. (July 16-18, 2008, Tainan, Taiwan)
    22. Cheng-Wu Lin and Soon-Jyh Chang, "An Automated Synthesis Tool for Fully Differential OPAMPs," Proceedings of the 18th VLSI Design/CAD Symposium. (August 7-10, 2007, Hualien, Taiwan)
    23. Hung-Yu Huang, Ying-Zu Lin, and Soon-Jyh Chang, "A 5-bit 1 GSample/s Two-Stage ADC with a New Flash Folded Architecture," Proceedings of the 18th VLSI Design/CAD Symposium. (August 7-10, 2007, Hualien, Taiwan)
    24. An-Sheng Chao, Soon-Jyh Chang, Shih-Ming Luo, Steven Huang, and Chih-Haur Huang, "Design and Implementation of a Built-in Self-Test Scheme for Phase Lock Loops," Proceedings of the 1st VLSI Test Technology Workshop. (July 26-27, 2007, Hsinchu, Taiwan)
    25. Heng-Yao Lin, Hui-Hsien Tsai, Bin-Da Liu, Jar-Ferr Yang, and Soon-Jyh Chang, "An Efficient Design-for-testability Scheme for 2-D Transform in H.264 Advanced Video Coders," Proceedings of the 17th VLSI Design/CAD Symposium. (August 8-11, 2006, Hualien, Taiwan)
    26. Zhen-Guo Ding, Hsin-Hung Ou, Soon-Jyh Chang, and Bin-Da Liu, "A Self-Calibrated Pipelined ADC with Open-Loop Constant Gain Amplifier," Proceedings of the 17th VLSI Design/CAD Symposium. (August 8-11, 2006, Hualien, Taiwan)
    27. Ying-Zu Lin and Soon-Jyh Chang, "A Digitally Calibrated CMOS Current-Voltage Feedback Transconductor with an 80-dB SFDR up to 100MHz," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
    28. Hsin-Wen Ting, Cheng-Wu Lin, Bin-Da Liu, and Soon-Jyh Chang, "A Reconfigurable Sinusoidal Signal Generator for Analog-to-Digital Converter Built-In Self-Test," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
    29. Yen-Ting Liu, Lih-Yih Chiou, and Soon-Jyh Chang, "Adaptive Clocking Dual Edge Sense-Amplifier Flip-Flop for Low Power System," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
    30. Jin-Fu Lin and Soon-Jyh Chang, "A 1.8-V 10-Bit 100 MS/S Pipelined ADC using Modified Time-Shifted CDS Technique," Proceedings of the 16th VLSI Design/CAD Symposium. (August 9-12, 2005, Hualien, Taiwan)
    31. Ying-Zu Lin and Soon-Jyh Chang, "A High-SFDR and Wide-Bandwidth CMOS Current-Voltage Feedback Transconductor," Proceedings of the 15th VLSI Design/CAD Symposium. (August 10-13, 2004, Kenting, Taiwan)
    32. Chih-Haur Huang, Soon-Jyh Chang, and Kuen-Jong Lee, "Design of High-Resolution Pipelined Analog-to-Digital Converters using Multiple-Phase Capacitor-Splitting Feedback Interchange Technique," Proceedings of the 15th VLSI Design/CAD Symposium. (August 10-13, 2004, Kenting, Taiwan)
    33. Kuen-Jong Lee, Soon-Jyh Chang, and Ruei-Shiuan Tzeng, "A Sigma-Delta Modulation Based BIST Scheme for A/D Converters," Proceedings of the 14th VLSI Design/CAD Symposium. (August 12-15, 2003, Hualien, Taiwan)
    34. Soon-Jyh Chang, Chung Len Lee, and Jwu E Chen, "Structural Fault Based Specification Reduction for Testing Analog Circuits," Proceedings of the 12th VLSI Design/CAD Symposium. (August 14-17, 2001, Kuansi, Hsinchu, Taiwan)
    35. Soon-Jyh Chang, Chung Len Lee, and Jwu E Chen, "Functional Test Pattern Generation for CMOS Operational Amplifier," Proceedings of the 7th VLSI Design/CAD Symposium, pp.65-68. (August 13-16, 1996, Shihmen Dam, Taoyuan, Taiwan)