2020 ITC-Asia Program At A Glance (with Hyperlinks)

Sept. 23 - Wednesday Sept. 24 - Thursday Sept. 25 - Friday
Registration 8:50-10:30
Opening & Keynote Speech
Keynote 1: Li-C. Wang
Keynote 2: Mark M. Tehranipoor
Keynote Speech
(Advanced Testing Forum I)

Keynote 3: Harry Chen
Keynote 4: Daniel Yang
Keynote 5: Hans Han
10:30-11:00 Coffee Break 10:30-11:00 Coffee Break
Plenary Panel
Holy-Grail of IC Testing
Sessions A3, B3, C3
A3: Advanced Testing Forum II
B3: Diagnosis
C3: (Invited) Special Topics in Hardware Security
12:15-13:30 Lunch Break 12:15-13:30 Lunch Break
Half-Day Tutorials
A0: CIM Testing
B0: Hardware Security
C0: Approximate Testing
Sessions A1, B1, C1
A1: (Invited) RF and PUF Testing
B1: (Invited) Towards System-Oriented Testing
C1: Improving Test Quality by Machine Learning
Sessions A4, B4, C4
A4: Advanced Testing Forum III
B4: Yield Enhancement
C4: Special Topics on Analog/Timing/Briding Faults
14:45-15:05 Coffee Break 14:45-15:05 Coffee Break
Sessions A2, B2, C2
A2: Advanced Testing Solution: Industry Perspectives
B2: (Invited) Advanced Testing and Security: EDA Perspectives
C2: Design of Reliable Memories
Sessions A5, B5, C5
A5: Advanced Testing Forum IV
B5: Test Generation and Fault Simulation
C5: Towarding Secure and Reliable Video/Speech/Biochip Applications

Welcome Reception
(Courtyard Taipei)
(Courtyard Taipei)

Keynotes and Plenary Panel will be held at Room 505a & 505b
Tutorial A0 and Sessions A1, A2, A3, A4, A5, A6 will be held at Room 505a
Tutorial B0 and Sessions B1, B2, B3, B4, B5, B6 will be held at Room 505b
Tutorial C0 and Sessions C1, C2, C3, C4, C5, C6 will be held at Room 505c

Sept. 23 – Wednesday, 13:30-16:20 pm
Half-Day Tutorials

Tutorial Co-Chairs: Prof. Soon-Jyh Chang (NCKU), H.-P. Charles Wen (NCTU) and Prof. Katherine Shu-Min Li (NSYSU)
In-memory computing (IMC) architecture has been considered as an alternative for overcoming the memory wall of von-Neumann computing architecture. Many IMC memories have been reported. They can be divided these into two types: RAM-based and nonvolatile-memory (NVM)-based IMC memories. The function and storage structure of an IMC memory are heavily dependent on the applications. Thus, the testing of IMC memories is much difficult than that of conventional memories. The testing of IMC memories should be executed in two different modes: memory mode and computing mode. However, some unique faults might only exist in computing mode and defect range of defects sensitized in memory mode and computing mode might be different. Therefore, fault modeling and test development should be done in two different operations modes. In this tutorial, we first review RAM-based and NVM-based IMC memories. Also, the testing concept of conventional RAMs is briefly reviewed. Then, existing fault modeling and testing techniques for RAM-based and NVM-based IMC memories are introduced.
Jin-Fu Li received the MS and PhD degrees, both in Department of Electrical Engineering, in 1999 and 2002 from National Tsing Hua University, Taiwan. He currently is a distinguished professor on the Department of Electrical Engineering, National Central University, and Associate Vice President for R&D of National Central University. His research interests include advanced VLSI design and test, memory testing and repair.
Dr. Li holds 16 patents and has published over 150 refereed papers. He was the 2008 recipient of CIEE Excellent Young Electrical Engineer Award, the 2010 recipient of TICD Distinguished Young Scholar Award, and the 2015 recipient of CIEE Outstanding Faculty Award of Electrical Engineering. He is actively involved in the international community as a member of the technical program committees of the leading conferences. He is a member of IEEE, has served on the editorial board of IEEE Design and Test since 2015.

While entering the new era of AIoT, hardware security has become an increasingly important research topic. As a key element for hardware security, physical(ly) unclonable function (PUF) has drawn attentions in many research fields. Benefiting from the inherent variability in electronic devices, a PUF can extract the underlying randomness and generate a unique fingerprint for an integrated circuit. The extracted randomness can be utilized as a root-of-trust (RoT) for hardware implementations that need security, such as an IoT device. This talk will begin with the basics of PUFs, including operation principle, PUF properties and circuit implementations. A wide variety of PUF implementations with different key features will be discussed, ranging from the early-developed SRAM PUFs, to the more recent quantum-tunneling PUFs. Furthermore, several PUF applications will be introduced, and we will explain why it is necessary for these applications to have a unique and reliable PUF. Finally, we will conclude this talk by going through a few examples of PUF-based security solutions, to show the real uses cases of PUFs and why it is truly an essential element for security applications.
Kai-Hsin “Kent” Chuang received his PhD degree in electrical engineering from KU Leuven, Belgium, in 2020. He joined the R&D division of PUFsecurity corporation, Taiwan, in 2020. Before joining his current company, he was working in the COSIC research group of KU Leuven and the reliability research group of imec, Belgium. His PhD research is about developing highly reliable PUF circuits in CMOS and emerging memory technologies. His current research interests include hardware root-of-trust, PUF-based security solutions, and attack/protection techniques for cryptographic implementations.

Improving yield/reliability of digital circuits is crucial for consumer products. Nevertheless, this may incur huge cost. In this tutorial we will show that by well exploiting the inherent tolerability of errors of humans or machines, the effective yield/reliability of digital multimedia processing circuits can be improved in a cost-effective manner. This is achieved by performing "approximate testing", which focuses on further classifying erroneous yet still acceptable computation results/chips in addition to the conventional binary testing results (go/no-go). We will talk about the developed approximate testing methods in the literature and their application scenarios. Pros and cons of these methods will also be discussed. In addition, we will also discuss the difference in error tolerability from the human and machine aspects, and the impacts on the development of approximate testing methods. This can lead to more significant yield/reliability improvement results. We hope this tutorial can motivate more further researches on this notion and its implementation as well as applications.
Tong-Yu Hsieh (S’05–M’10) received the B.S. and Ph.D. degrees in electrical engineering from National Cheng Kung University, Tainan, Taiwan, in 2004 and 2009, respectively.,He was also a Visiting Scholar with the Department of Electrical Engineering, University of Southern California, Los Angeles, CA, USA, from 2008 to 2009. He joined as a Faculty Member with the National Sun Yat-sen University, Kaohsiung, Taiwan, in 2011, and is currently an Associate Professor with the Department of Electrical Engineering. His current research interests include very large scale integration (VLSI) design and testing, VLSI reliability, and yield improvement. He has been a member of IEEE Circuits and Systems Society since 2005.

Sept. 24 – Thursday, 8:50-10:30 am
Keynote Speech

Keynote Co-Chairs: Prof. Ming-Der Shieh (NCKU) and Prof. Shi-Yu Huang (NTHU)
Applying machine learning to improve test data analytics has been a hot topic in recent years. This talk presents the idea of Intelligent Engineering Assistant (IEA) in view of applying machine learning in test data analytics. IEA is an AI agent that can act as a surrogate for an engineer to perform a specific analytics task. IEA is an autonomous system where the executable workflow component is enabled with machine learning models capturing human perception. In other words, machine learning is employed in IEA to model human perception and to enable automation of the workflow. Using analytics on wafer plots as an example, this talk presents various ideas and an IEA platform to apply machine learning which enables plot-based analytics in applications to actual semiconductor chip product lines.
Li-C. Wang, is a professor of the ECE department and the Chair of Computer Engineering program at University of California, Santa Barbara. He received PhD in 1996 from University of Texas at Austin, and was previously with Motorola PowerPC Design Center until 2000. Since 2003, his research has been focusing on machine learning specifically for applications in EDA and Test. He received 9 Best Paper Awards from major conferences, including the more recently from ITC 2014, ITC 2019, VLSI DAT 2019 and VTS 2016. He is the recipient of the 2010 Technical Excellence Award from SRC and the recipient of the 2017 IEEE TTTC Bob Madge Innovation Award. He is a fellow of IEEE, and was the General Chair of the International Test Conference (ITC) in 2017 and 2018.

Design, fabrication, assembly, test, and debug of integrated circuits and systems have become distributed across the globe, raising major concerns about their security and trustworthiness. Such systems are prevalent is many critical-mission infrastructures, in which they require long and secure operation life. In this talk, we will provide a detailed overview of the challenges in today’s global electronics supply chain, then discuss the need for establishing hardware root of trust within cyber domain. Notably, we will present innovative methods to demonstrate authentication and trust verification for integrated circuits and systems during their lifecycle.
Mark Tehranipoor is currently the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the ECE Department, University of Florida. He is currently serving as Director for Florida Institute for Cybersecurity Research (FICS), National Microelectronics Security Training Center (MEST), CYAN Center of Excellence, and ECI Transition Center. He is also serving as Program Director of Cybersecurity for UF Herbert Wertheim College of Engineering. His current research interests include: IoT security, hardware security and trust, supply chain risk management and security, counterfeit electronics detection and prevention and reliable circuit design. Dr. Tehranipoor has published over 400 journal articles and refereed conference papers and has given more than 200 invited talks and keynote addresses. He has 8 patents, 20+ pending, and has published 11 books and 22 book chapters. He is a recipient of 13 best paper awards and nominations, as well as the 2008 IEEE Computer Society (CS) Meritorious Service Award, the 2012 IEEE CS Outstanding Contribution, the 2009 NSF CAREER Award, and the 2014 MURI award. His projects are sponsored by both the industry (Semiconductor Research Corporation (SRC), Texas Instruments, Freescale, Comcast, Honeywell, LSI, Avago, Mentor, A Siemens Business, R3Logic, Cisco, Qualcomm, Raytheon, MediaTeck, etc.) and Government (NSF, ARO, MDA, DOD, AFOSR, DOE, AFRL, DARPA, Draper, etc.).
He serves on the program committee of more than a dozen leading conferences and workshops. He served as Program and General Chairs of several leading conferences and workshops. He co-founded IEEE International Symposium on Hardware-Oriented Security and Trust (HOST) and served as HOST-2008 and HOST-2009 General Chair ( He is currently serving as HOST’s Chair of Steering Committee. He is also the co-founder of Trust-Hub (, IEEE Asian HOST (, and IEEE Int. Conf. on Physical Assurance and Inspection of Electronics (PAINE). He serves as co-EIC for Journal on Hardware and Systems Security (HaSS). He also served as an Associate EIC for IEEE Design & Test, an IEEE Distinguished Speaker, and an ACM Distinguished Speaker from 2010 to 2014. He is currently serving as an Associate Editor for JETTA, IEEE D&T, JOLPE, Transactions on VLSI (TVLSI), Transactions on Computer, and Transactions on Design Automation for Electronic Systems (TODAES). He has served as IEEE Ambassador on Cybersecurity. Prior to joining University of Florida, Dr. Tehranipoor served as the founding director of the Center for Hardware Assurance, Security, and Engineering (CHASE) and the Comcast Center of Excellence in Security Innovation (CSI) at the University of Connecticut. Dr. Tehranipoor is a Fellow of IEEE, a Golden Core Member of the IEEE, and Member of ACM and ACM SIGDA.

Sept. 24 – Thursday, 11:00-12:15 am
Plenary Panel

Panel Co-Chairs: Prof. Shi-Yu. Huang (NTHU) and Prof. Li-C. Wang (UCSB)
Topic: Holy-Grail of IC Testing


Harry Chen
Thomas Lai
H.-P. Charles Wen
National Chiao Tung U.
Brian Sung
Ting-Pu Tai
Dragon Hsu
Mentor, A Siemens Business

Semiconductor industry is seeing one of the biggest booms in history, driven by various technologies like AI, 5G, Automotive, Internet of Things, and High-Performance Cloud Computing, etc. Amid this tsunami of technology revolution, an IC is anticipated to be more than itself – it has to be not just more powerful, but also more reliable, more longer-lasting, and more secure. Very often, it is integrated by a number of heterogeneously made functional dies. Are we “test community” there yet for these challenges? Let’s hear from the experts from both the academia and industry, and together we debate our future roadmap leading to the Holy-Grail if there exists one.

Sept. 24 – Thursday, 13:30-14:45 pm
Session A1: (Invited) RF and PUF Testing

Session Chair: Prof. Soon-Jyh Chang (NCKU)

A1-1: Cost Effective RF Test for MCU/IoT Chip
Eugene Lin, Chroma ATE Inc.

A1-2: A novel PUF Scheme and the Paradox of PUF Testing
Emory Liu, Product Portfolio Manager of Market Development Department, eMemory

A1-3: A PUF Design Embeddeed in a SAR ADC
Hsin-Ta Chien, National Cheng Kung University

Sept. 24 – Thursday, 13:30-14:45 pm
Session B1: (Invited) Towards System-Oriented Testing

Session Chair: Dr. Harry Chen (Meditek Inc.)

B1-1: Heterogeneous Integration Roadmap, Test Technology Working Group Update
Dave Armstrong, HIR Test TWG Chairman, Director of Business Development, Advantest.

B1-2: System Introspection, Embedded Analytics and Data
Gajinder Panesar, Fellow, Mentor, A Siemens Business

B1-3: Solving Next Generation SLT Test Challenges
Herbert Tsai, Chroma ATE Inc.

Sept. 24 – Thursday, 13:30-14:45 pm
Session C1: Improving Test Quality by Machine Learning

Session Chair: Prof. H.-P. Charles Wen (NCKU)

C1-1: Site-aware Anomaly Detection with Machine Learning for Circuit Probing to Prevent Overkill
Mincent Lee, Cheng-Tse Lu, Chia-Heng Tsai, Hao Chen and Min-Jer Wang, Taiwan Semiconductor Manufacturing Company, Ltd.

C1-2: Automatic IR-Drop ECO Using Machine Learning
Heng-Yi Lin, Yen-Chun Fang, Shi-Tang Liu, Jia-Xian Chen, James Chien-Mo Li and Eric Jia-Wei Fang, National Taiwan University and MediaTek, Taiwan

C1-3: A Deep Learning-Based Screening Method for Improving the Quality and Reliability of Integrated Passive Devices
Chien-Hui Chuang, Kuan-Wei Hou and Cheng-Wen Wu, National Tsing Hua Univ., Taiwan

Sept. 24 – Thursday, 15:05-16:20 pm
Session A2: Advanced Testing Solution: Industry Perspectives

Session Chair: Prof. Hao-Chiao Hong (NCTU)

A2-1: Test Challenges of Providing Low Phase Noise Reference Clock Signal with ATE Platform
Kevin Fan, Advantest Inc.

A2-2: Development and Validation of a Novel Reliable Method for Wet Testing on Biochemical Chip
Po-Ting Lai, Yu-Hao Ciou, Chieh-Wen Lu, Kuang-Hsiang Liu, Tung-Liang Chiu and Wendy Chen, King Yuan Electronics Co., Ltd

A2-3: Novel Circuit Probing for Tiny Inductor
Chia-Heng Tsai, Chi-Chang Lai, Hao Chen and Min-Jer Wang, Taiwan Semiconductor Manufacturing Company, Ltd.

Sept. 24 – Thursday, 15:05-16:20 pm
Session B2: (Invited) Advanced Testing and Security: EDA Perspectives

Session Chair: Prof. Jiun-Lang Huang (NTU)

B2-1: Advancing Test to the Physical Dimension
Vivek Chickermane, Distinguished Engineer & Sr Group Director of R&D, Modus DFT Software Dept., Cadence Design Systems

B2-2: Data Analytics Solutions for IC Manufacturing and Test Excellence
Howard Chen and Caros Chu, Program Manager and Application Manager, Synopsys Design Group

B2-3: Silicon Lifecycle Solutions for Security, Safety and Optimisation
Aileen Ryan, Sr. Director of Strategy, Mentor, A Siemens Business

Sept. 24 – Thursday, 15:05-16:20 pm
Session C2: Design of Reliable Memories

Session Chair: Prof. Shyue-Kung Lu (NTUST)

C2-1: Design of a Highly Reliable SRAM Cell with Advanced Self-Recoverability from Soft Errors
Aibin Yan, Jun Zhou, Yuanjie Hu, Yan Chen, Tianming Ni, Jie Cui, Patrick Girard and Xiaoqing Wen, Anhui University, University of Montpellier/CNRS, and Kyushu Institute of Technology

C2-2: Refresh Power Reduction of DRAMs in DNN Systems Using Hybrid Voting and ECC Method
Tsung-Fu Hsieh, Jin-Fu Li, Jenn-Shiang Lai, Chih-Yen Lo, Ding-Ming Kwai, and Yung-Fa Chou, National Central University and ITRI, Taiwan

C2-3: ECC Caching Techniques for Protecting NAND Flash Memories
Shyue-Kung Lu and Zeng-Long Tsai, National Taiwan University of Science and Technology

Sept. 25 – Thursday, 8:50-10:30 am
Keynote Speech
(Advanced Testing Forum I)

Keynote Chair: Mr. Roger Hwang (ASE Group)
1. 5G-enabled mobile phones are starting to be delivered to consumers in high volume.
2. As consumers migrate from 4G to 5G to enjoy enhanced capabilities, pricing expectations do not rise accordingly.
3. Yet 5G technology is significantly more complex than previous generations, especially in the radio front-end.
4. 5G testing also becomes more complex across all production stages from wafer, to package, to system test.
5. Innovative ideas and approaches need to be developed across the supply chain through collaborations to keep test costs reasonable and ensure good profit margins.

Harry Chen is currently IC Testing Scientist at MediaTek. Besides research in advanced testing topics such as defect modeling and end-to-end test data analytics, he helps promote quality-related concepts throughout the company and with key suppliers and customers. Harry actively participates in test-related conferences such as ITC, ATS, ETS, VTS, and VLSI-DAT by serving on program committees, publishing papers, and giving talks. Harry is a core member of SEMI Taiwan Testing Committee. He also leads the System-Level Test focus group in the international Heterogeneous Integration Roadmap collaborative effort. Prior to MediaTek, Harry held technical positions at Analog Devices and Cadence Design Systems.

1. Testing for System Integration Technology
2. Advanced Testing Requirement
3. Integrated Testing Service
4. Summary

Director, TSMC

1. Industrial 4.0 Evolution
2. 9 Technologies Transforming Industrial Production
3. Smart Manufacturing in backend Test Process KYEC
4. Are you ready for Smart Manufacturing transforming?

1. B.S and Master degree in E.E, NTTU.
2. In charge of LAN/Networking products testing and verification @ Acer.
3. Invent VC-20 voice compression card with DSP uP per master degree's thesis, @Quanta computer Inc.
4. Program/Load Board development, Platform program conversion, @Microchip Inc.
5. In charge of FT(Final Test) production line @Walton Advanced Engineering Inc
6. In charge of manufactory center @King Yuan Electronics Cop.
7. Got 15 patents from past 30+ years experience..

Sept. 25 – Friday, 11:00-12:15 am
Session A3: Advanced Testing Forum II

Session Chair: Mr. Roger Hwang (ASE Group)

A3-1: Design for Manufacturing Test in Automotive Radar applications
Robert van Rijsinge, Engineering Manager, NXP Semiconductors Taiwan Ltd.

A3-2: Moving beyond structural & functional testing to parametric testing using Deep Data analytics
Alex Burlak, Vice President, ProteanTecs

A3-3: The challenge of 5G RF Test under Heterogeneous Integration
Eric Wu, Vice President of Advanced Test Engineering, Siliconware Precision Industries Co., Ltd.

Sept. 25 – Friday, 11:00-12:15 am
Session B3: Diagnosis

Session Chair: Prof. James Chien-Mo Li (NTU)

B3-1: Diagnosis technique for Clustered Multiple Transition Delay Faults
Yan-Shen You, Chih-Yan Liu, Mu-Ting Wu, Po-Wei Chen and James Chien-Mo Li, National Taiwan University

B3-2: Adaptive Test Pattern Reordering for Diagnosis using k-Nearest Neighbors
Chenlei Fang, Qicheng Huang and Ronald Blanton, Carnegie Mellon University

B3-3: Diagnosis Outcome Prediction on Limited Data via Transferred Random Forest
Qicheng Huang, Chenlei Fang and Shawn Blanton, Carnegie Mellon University

Sept. 25 – Friday, 11:00-12:15 am
Session C3: (Invited) Special Topics in Hardware Security

Session Co-Chairs: Prof. Asadi Zanjani, Navid (U. of Florida) and Prof. Soon-Jyh Chang (NCKU)

C3-1: Software Assistant for Hardware Security
Li-C Wang, University of California Santa Barbara

C3-2: On Optical Attacks Making Logic Obfuscation Fragile
Navid Asadi Zanjani, University of Florida

C3-3: A Novel Tampering Attack on AES Cores with Hardware Trojans
Ujjwal Guin, Auburn University

Sept. 25 – Friday, 13:30-14:45 pm
Session A4: Advanced Testing Forum III

Session Chair: Dr. Ching Cheng Tien (Sigurd Corporation)

A4-1: Tester Architecture for Era of AI & Big Data
Gregory Smith, President, Teradyne Inc.

A4-2: Semiconductor Test Paradigm Shift
Chandran Nair, CEO, AEM Holdings Ltd.

A4-3: 3H probe card by AI
Michael Li, Deputy Chief Engineer, Chunghwa Precision Test Tech. Co., Ltd.

Sept. 25 – Friday, 13:30-14:45 pm
Session B4: Yield Enhancement

Session Chair: Prof. Jin-Fu Li (NCU)

B4-1: High Efficiency and Low Overkill Testing for Probabilistic Circuits
Ming-Ting Lee, Chen-Hung Wu, Shi-Tang Liu, Cheng-Yun Hsieh and James Chien-Mo Li, National Taiwan University

B4-2: The Decision Mechanism Uses the Multiple-Tests Scheme to improve Test Yield in IC Testing
Chung-Huang Yeh and Jwu E Chen, National Central University, Taiwan

B4-3: W-ERA: One-Time Memory Repair with Wafer-Level Early Repair Analysis for Cost Reduction
Hayoung Lee, Donghyun Han, Hogyeong Kim and Sungho Kang, Yonsei University, Korea

Sept. 25 – Friday, 13:30-14:45 pm
Session C4: Special Topics on Analog/Timing/Briding Faults

Session Chair: Prof. Mango Chia-Tso Chao (NCTU)

C4-1: Modified BER Test for SAR ADCs
Chia-Chuan Lee and Soon-Jyh Chang, National Cheng Kung University, Taiwan

C4-2: Test Methodology for Defect-based Bridge Faults
Yu-Pang Hu, Shuo-Wen Chang, Kai-Chiang Wu, Chi-Chun Wang, Fu-Sheng Huang, Yi-Lun Tang, Yung-Chen Chen, Ming-Chien Chen and Mango Chao, National Chiao Tung University and Novatek Microelectronics Corp., Taiwan

C4-3: Path Delay Measurement with Correction for Temperature and Voltage Variations
Yousuke Miyake, Takaaki Kato and Seiji Kajihara, Kyushu Institute of Technology, Japan

Sept. 25 – Friday, 15:05-16:20 pm
Session A5: Advanced Testing Forum IV

Session Chair: Dr. Ching Cheng Tien (Sigurd Corporation)

A5-1: Improve Workflow Optimization and Analytics from Design to Test
George Zafiropoulos, Vice President, National Instruments

A5-2: Testing in the Age of Exascale Computing
Ralf Stoffels, Vice President of Marketing, Advantest Corporation

Sept. 25 – Friday, 15:05-16:20 pm
Session B5: Test Generation and Fault Simulation

Session Chair: Prof. Jing-Jia Liou (NTHU)

B5-1: GPU-based Hybrid Parallel Logic Simulation for Scan Patterns
Liyang Lai, Qiting Zhang, Hans Tsai and Wu-Tung Cheng, Shantou University and Mentor, A Siemens Business

B5-2: DSSP-ATPG: A Deterministic Search-Space Parallel Test Pattern Generator
Kuen-Wei Yeh and Jiun-Lang Huang, National Taiwan University

B5-3: Estimation of Test Data Volume for Scan Architectures with Different Numbers of Input Channels
Fong-Jyun Tsai, Chong-Siao Ye, Yu Huang, Kuen-Jong Lee, Wu-Tung Cheng, Sudhakar Reddy, Mark Kassab, Janusz Rajski, and Shi-Xuan Zheng, National Cheng Kung University, HiSilicon Technologies, Mentor, A Siemens Business, University of Iowa

Sept. 25 – Friday, 15:05-16:20 pm
Session C5: Towarding Secure and Reliable Video/Speech/Biochip Applications

Session Chair: Prof. Tong-Yu Hsieh (NSYSU)

C5-1: On Enhancing Error-Tolerability of Videos via Re-Encoding with Adaptive I-Frame Insertion
Tong-Yu Hsieh, Chen-Chia Chung and Run-Tsung Wu, National Sun Yat-sen University, Taiwan

C5-2: A Self-Detection and Self-Repair Methodology for Reliable Speech Recognition Considering AWGN Noises
Tong-Yu Hsieh and Yu-Min Chung, National Sun Yat-sen University, Taiwan

C5-3: Watermarking for Paper-Based Digital Microfluidic Biochips
Jian-De Li, Sying-Jyan Wang, Katherine Shu-Min Li and Tsung-Yi Ho, National Chung-Hsing University, National Sun Yat-Sen University, National Tsing Hua University, Taiwan